The present disclosure relates to command bus training, and more particularly, to a memory device and system supporting command bus training, and an operating method thereof.
To support a high speed interface with a memory device, a memory controller may provide a clock signal to the memory device. The memory device may process signals received from the memory controller in response to the clock signal received from the memory controller, and may synchronize signals to be transmitted to the memory controller with the clock signal. Due to demands for a high data transmission speed, a frequency of a clock signal provided from the memory controller may increase. Also, it has become important to accurately capture signals transferred between the memory controller and the memory device. Thus, the memory device and the memory controller may typically implement a bus training method.